The present invention relates to semiconductor devices, and more particularly comprises semiconductor devices which include junctions that rectify when the semiconductor is doped either N or P-type by either metallurgical or field induced means, as well as similar means for limiting parasitic current flow in semiconductor substrates. Semiconductor substrates can, prior to the fabrication of present invention semiconductor devices therein, be essentially intrinsic, or substantially homogeneously contain N and P-type dopants at substantially equal levels, (ie. compensated), or simultaneously substantially homogeneously contain N and P-type dopants at different levels, or be doped a single N or P doping type, and can include functional combinations thereof. A preferred embodiment is formed in intrinsic or substantially compensated semiconductor and is a simple to fabricate single device which provides operational characteristics similar to conventional dual device CMOS, under described biasing schemes.
MOSFETS, CMOS, gate voltage controlled direction of rectification, and single device inverting and single device non-inverting MOS semiconductor devices which demonstrate operating characteristics similar to those of multiple device Complementary Metal Oxide Semiconductor (CMOS) systems have been previously described in U.S. Pat. No. 5,663,584 to Welch, and said 584 Patent is incorporated hereinto by reference. Semiconductor devices described in said 584 Patent operate on the basis that materials exist which produce a rectifying junction with semiconductor channel regions when they are doped either N or P-type, whether said doping is achieved via metallurgical or field induced means. Said materials typically form junctions that are termed xe2x80x9cSchottky barrierxe2x80x9d junctions with semiconductors, (in contrast to P-N Junction), however, said terminology is not to be considered limiting to the present invention based upon technical definitions of the terminology xe2x80x9cSchottky barrierxe2x80x9d, and where the terminology xe2x80x9cSchottky barrierxe2x80x9d junction is utilized in this Disclosure it is to be understood that it is used primarily to distinguish a junction described thereby from xe2x80x9cP-Nxe2x80x9d junctions, and more particularly to identify junctions between a semiconductor and element(s) which are rectifying whether N or P-type Doping is present in the semiconductor, and whether said doping is present as the result of metallurgical or field induced means.
Another U.S. Pat. No. 5,760,449 to Welch describes Source Coupled Regeneratively Switching CMOS formed from a seriesed combination of N and P-Channel MOSFTES which each demonstrate the special operating characteristics of conducting significant current flow only when the Drain and Gate of a 449 Patent MOSFET are of opposite polarity, and the Gate polarity is appropriate to invert a channel region. Said 449 Patent is incorporated hereinto by reference, as is U.S. Pat. No. 6,091,128 to Welch, (which describes prevention of parasitic current flow in semiconductor substrates), and provisional Applications and Ser. Nos. 60/081,705 and 60/090,565. Also disclosed are Patents to Lepselter, U.S. Pat. No. 4,300,152; Koeneke et al., U.S. Pat. No. 4,485,550; Welch, U.S. Pat. No. 4,696,093; Mihara et al., U.S. Pat. No. 5,049,953; Homna et al. U.S. Pat. No. 5,177,568; and Nowak, U.S. Pat. No. 5,250,834. A Japanese Patent to Shirato, No. 04056360 is also disclosed as it describes the presence of conducting material in a MOSFET Channel region, (in contrast to a current limiting material as in the present invention).
A relevant article titled xe2x80x9cSB-IGFET: An Insulated Gate Field Effect Transistor using Schottky Barrier Contacts for Source and Drainxe2x80x9d, by Lepselter and Sze, Proc. IEEE, 56, January 1968, pp. 1400-1402, is also identified in said 584 Patent. Further, a paper by Lebedov and Sultanov, titled xe2x80x9cSome Properties of Chromim-Doped Siliconxe2x80x9d, Soviet Physics, Vol. 4, No. 11, May 1971 is identified as it discusses formation of a rectifying junction by diffusion of chromium into P-type Silicon. A paper by Hogeboom and Cobbold, titled xe2x80x9cEtched Schottky Barrier MOSFETS Using A Single Mask, Electronics Letters, Vol. 7, No. 5/6, (March 1971) is also included as it describes formation of Schottky barrier MOSFETS by deposition of Aluminum onto semiconductor. Articles which are incorported by reference hereinto, and which describe fabrication of non-scale conventional Schottky-barrier MOSFETS are xe2x80x9cSub-40 nm PtSi Schottky Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistorsxe2x80x9d, Wang, Snyder and Tucker, Appl. Phys. Lett., Vol. 74, No. 8, (Feb. 22, 1999); and xe2x80x9cExperimental Investigation of a PtSi Source and Drain Filed Emission Transistorxe2x80x9d, Synder, Helms and Nishi, Appl. Phys. Lett. 67(10) (Sep. 4, 1995). While not being a point of Patentability, it is to be understood that present invention systems whixe2x80x9cSub-40 nm PtSi Schottky Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistorsxe2x80x9d, Wang, Snyder and Tucker, Appl. Phys. Lett., Vol. 74, No. 8, (Feb. 22, 1999); and xe2x80x9cExperimental Investigation of a PtSi Source and Drain Filed Emission Transistorxe2x80x9d Synder, Helms and Nishi, Appl. Phys. Lett. 67(10) (Sep. 4, 1995). ch incorporate sidewall spacers, as taught in said directly foregoing references, are to be considered within the scope of the present invention as claimed. Also mentioned, and included herein by reference for general insight to semiconductor circuits and systems, is a book titled xe2x80x9cMicroelectronic Circuitsxe2x80x9d by Sedra and Smith, Saunders College Publishing, 1991. Likewise mentioned, and included herein by reference for the purpose of providing insight into semiconductor device fabrication, is a book titled xe2x80x9cPhysics and Technology of Semiconductor Devicesxe2x80x9d, by Grove, John Wiley and Sons, 1967; and a book titled xe2x80x9cElectronic Materials Science: For Integrated Circuits in Si and GaAsxe2x80x9d, Mayer and Lau, MacMillan, 1990.
Even in view of the cited Welch U.S. Pat. Nos. 5,663,584; 5,760,449 and 6,091,128 Patents, and co-pending CIP applications derived therefrom which describe inverting and non-inverting single device equivalents to conventional CMOS, regeneratively switching N and P-Channel source coupled CMOS, and the blocking of parasitic current flows in semiconductor systems by use of material which forms rectifying junctions with either N or P-type semiconductor whether said doping is metallurgically or field induced; there remains need for clarification and description of parasitic current limitation, and of biasing and switching operational characteristics of single device equivalents to CMOS, particularly where essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels; essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; and containing a single metallurgical doping type, substantially compensated, or lightly doped, semiconductor is beneficially utilized as semiconductor substrate material.
The present invention is primarily a semiconductor device in a semiconductor substrate, comprising at least one junction which is formed by introduction of typically, (though not necessarily), non-semiconductor substrate material(s) to said semiconductor substrate, wherein said typically non-semiconductor substrate material(s) form a rectifying junction with either N and P-type semiconductor, whether said doping is metallurgically or field induced. Said non-semiconductor components can be any functional material(s) or dopants entered to a semiconductor substrate by, for instance, a procedure comprising vacuum deposition, ion-implantation and/or pre-deposition and diffusion, each accompanied by appropriate annealing. And, it is noted that the semiconductor substrate can, prior to the fabrication of present invention semiconductor devices therein, be initially essentially intrinsic or substantially homogeneously contain metallurgical N and P-type dopants at substantially the same levels, (ie. be substantially compensated), or be doped single metallurgical N or P-type, or substantially homogeneously contain metallurgical N and P-type dopants at different levels, (eg. within two (2) or three (3) orders of magnitude of one another), or be metallurgically doped a single N or P-type, and can be functional combinations of said substrate types, (eg. there can be regions containing N and/or P-type dopant(s) in an intrinsic substrate, for instance).
Most importantly, the present invention comprises inverting and non-inverting devices with operating characteristics similar to dual device seriesed N and P-Channel MOSFETS CMOS systems. In use said inverting and non-inverting present invention devices, comprise two oppositely facing electrically interconnected rectifying diodes in a region of a semiconductor substrate which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), and functional combinations thereof. Any functional semiconductor substrate is within the scope of the present invention. A basic feature of present invention devices is that a forward direction of rectification of each of said electrically interconnected oppositely facing rectifying diodes changes depending upon what doping type, (N or P), be it metallurgically or field induced, is present in the semiconductor. Said present invention inverting and non-inverting single device equivalents to dual device seriesed N and P-Channel MOSFETS CMOS systems further comprise gate means for field inducing effective doping type in said semiconductor, said gate means being set off from said semiconductor by insulator, and each has a non-electrically interconnected terminal. In use, different voltages are applied to the non-electrically interconnected terminals of each of the oppositely facing rectifying diodes, and a voltage between said applied different voltages, inclusive, is monitored at the electrical interconnection between said two oppositely facing rectifying diodes, which monitored voltage responds as a function of applied gate voltage. Said monitored voltage is essentially electrically isolated from said gate voltage and appears at said electrical interconnection between said two oppositely facing rectifying diodes primarily through the rectifying diode which is caused to be forward biased as a result of semiconductor xe2x80x9cdoping typexe2x80x9d affected by said applied gate voltage. The basis of operation of said inverting and non-inverting gate voltage channel induced semiconductor devices being that said rectifying junctions are each comprised of material(s) that form a rectifying junction to semiconductor substrate when it is doped either N or P-type by either metallurgical or field induced means.
To aide with understanding of the present invention, an embodiment of an inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, similar to that disclosed in U.S. Pat. No. 5,663,584 and continuations therefrom, is described directly herein. Said inverting gate voltage channel induced semiconductor device is typically, though not necessarily, formed in a surface region of a single doping type, (ie. no requirement of alternating P and N-type regions), semiconductor substrate which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), and functional combinations thereof; and comprises two junctions, termed source and drain, which are separated by a first semiconductor channel region, and further comprises two additional junctions, termed source and drain, which are separated by a second semiconductor channel region. Gates, to which semiconductor channel region effecting voltage can be applied, are associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use, application a sufficient positive voltage to said gates will attract electrons to said first and second semiconductor channel regions, and application of sufficient negative voltage to said gates will attract holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each essentially non-rectifying, and which drain junctions are rectifying junctions. Said rectifying junctions can each be a Schottky barrier junction comprising a semiconductor and non-semiconductor component. However, any junction which performs the function required, (ie. the formed junction is rectifying when either N or P-type doping is present in the semiconductor, whether metallurgical or field induced), is within the scope of the present invention, emphasis added. And, it is specifically to be understood that such junctions can be formed by ion implantation, or diffusion procedures as reported by Lebedev and Sultanov in the reference thereby cited in the Background Section herein, which reference disclosed diffusion chromium into P-type Silicon and thereby formed rectifying junctions. (It is to be understood, that where ion implantation or diffusion etc. techniques are applied to place junction forming material(s) into a semiconductor, the resulting.junctions can still be described as being Schottky barriers, perhaps not in the standard sense of being a metal directly bonded to a semiconductor, but in the sense that a material forms a rectifying junctionxe2x80x94other than a P-N junctionxe2x80x94in said semiconductor. Also, even where a metal is deposited onto a semiconductor, and annealing is applied to the resulting system, some diffusion of the deposited metal per se. can occur into the semiconductor or a compound can form which extends into the semiconductor, leaving the boundary between what is purely a Schottky barrier and what involves a diffusion formed junction a bit xe2x80x9cgreyxe2x80x9d).
Continuing, in the directly following, for purposes of description, said rectifying junctions are assumed to be Schottky barrier junctions comprising semiconductor and non-semiconductor components, and a non-semiconductor component of the rectifying Schottky barrier drain junction associated with said first semiconductor channel region of said inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, is electrically interconnected with a non-semiconductor component of the rectifying Schottky barrier drain junction associated with said second semiconductor channel region, and said gates associated with the first and second channel regions are electrically interconnected. During operation the electrically non-interconnected essentially non-rectifying source junctions are held at different voltages, and application of a gate voltage affects semiconductor channel region doping type in both said first and second channel regions, and thus which electrically interconnected rectifying Schottky barrier drain junction forward conducts and which does not forward conduct, thereby controlling the voltage present at the non-semiconductor components of the electrically interconnected Schottky barrier drain junctions essentially through said forward conducting rectifying semiconductor Schottky barrier junction. In said inverting gate voltage channel induced semiconductor device an increase in applied Gate voltage leads to a decrease in the voltage present at the non-semiconductor components of the electrically interconnected Schottky barrier drain junctions, which can be accessed via a junction thereto. It is to be noted that said non-semiconductor components of said Schottky barrier drain junctions are present xe2x80x9cbetweenxe2x80x9d said first and second channel regions, as said term xe2x80x9cbetweenxe2x80x9d is utilized herein, (ie. electrically between). (Note, special discussion of operational bias characteristics of inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, particularly when formed in essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, (and where a constant polarity voltage source is applied across the electrically non-interconnected essentially ohmic junctions is utilized), is found in the Detailed Description of this Disclosure).
Particularly where an inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems is formed in essentially essentially intrinsic or substantially compensated semiconductor, the operational description is beneficially slightly revised. Said inverting gate voltage channel induced semiconductor device formed an essentially intrinsic or substantially compensated semiconductor substrate still comprises two junctions, termed source and drain, which are separated by a first semiconductor channel region, and still further comprises two additional junctions, termed source and drain, which are separated by a second semiconductor channel region. Gates, to which semiconductor channel region effecting voltage can be applied, are still associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use application of sufficient positive voltage to said gates still attracts electrons to said first and second semiconductor channel regions, and application of sufficient negative voltage to said gates still attracts holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions. However, the source junctions are each essentially non-rectifying only when sufficient gate voltage induced doping is present in the channel region adjacent thereto, and the drain junctions are rectifying (Schottky barrier) junctions only when sufficient gate voltage induced doping is caused to be present in the channel region adjacent thereto. Again assuming said xe2x80x9cpotentiallyxe2x80x9d rectifying junctions are Schottky barrier junctions and each comprises semiconductor and non-semiconductor components, a non-semiconductor component of the xe2x80x9cpotentiallyxe2x80x9d rectifying (Schottky barrier) drain junction associated with said first semiconductor channel region is again electrically interconnected with a non-semiconductor component of the xe2x80x9cpotentiallyxe2x80x9d rectifying (Schottky barrier) drain junction associated with said second semiconductor channel region, and said gates are again electrically interconnected. During operation the electrically non-interconnected xe2x80x9cpotentiallyxe2x80x9d essentially non-rectifying source junctions are held at different, preferably same polarity, voltages. Said voltages can be selected from the group consisting of: (positive and negative with respect to ground inclusive of ground). Application of a gate voltage selected from the group consisting of: (positive and negative), affects semiconductor channel region doping type in said first and second channel regions to be a selection from the group consisting of: (essentially non-conductive essentially intrinsic and substantially compensated and doped to the same type selected from the group consisting of: (n-type and p-type), at doping levels selected from the group consisting of: (essentially equal and different in said first and second channels)). Thus is determined which.electrically interconnected rectifying (Schottky barrier) drain junction forms in said otherwise essentially intrinsic or substantially compensated semiconductor substrate and forward conducts, thereby controlling the voltage present at the non-semiconductor components of the electrically interconnected (Schottky barrier) drain junctions essentially through said formed forward conducting rectifying semiconductor (Schottky barrier) junction. The basis of operation is that essentially intrinsic or substantially compensated semiconductor is essentially non-conductive but that said (Schottky barrier) junctions associated with said first and second semiconductor channel regions are comprised of material(s) that form a rectifying junction to a semiconductor channel region when it is caused to be doped either N or P-type by field induced means. It is to be understood that the semiconductor substrate channel region and adjacent (Schottky barrier) junction which is not forward conducting can be characterized as a selection from the group consisting of: (being an essentially essentially intrinsic or substantially compensated channel region; being functionally comprised of two regions across which voltage can drop, namely an onset of pinch-off region and an essentially essentially intrinsic or substantially compensated channel region; and being functionally comprised of three regions across which voltage can drop, namely an onset of pinch-off region, a portion of the channel region which is populated with some gate voltage induced carriers, and a reverse biased (Schottky barrier) junction). Additionally, the semiconductor substrate channel region and adjacent (Schottky barrier) junction which is forward conducting can be characterized as comprising a doped channel region and a forward biased (Schottky barrier) junction.
Of course operation of inverting gate voltage channel induced semiconductor devices with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems formed in a lightly doped single doping type semiconductor is essentially similarly described, or finds description inherent in a combination of said foregoing descriptions of single device equivalent to CMOS formed in doped and in essentially essentially intrinsic or substantially compensated semiconductor.
A non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems is formed in a single doping type, (ie. no requirement of both N and P-type regions), semiconductor substrate which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), or functional combinations thereof; and comprises two junctions, termed source and drain, which are separated by a first semiconductor channel region, and further comprises two additional junctions, termed source and drain, which are separated by a second semiconductor channel region. Gates to which semiconductor channel region effecting voltage can be applied are associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use, application a sufficient positive voltage to said gates will attract electrons to said first and second semiconductor channel regions, and application of sufficient negative voltage to said gates will attract holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each essentially non-rectifying, and which drain junctions are rectifying (Schottky barrier) junctions. Again, for purposes of discussion, assuming the rectifying junctions are Schottky barrier junctions which each comprise a semiconductor and non-semiconductor component, in the non-inverting gate voltage channel induced semiconductor device the non-rectifying source junction associated with said first channel region and the non-rectifying source junction associated with the second channel region are electrically interconnected, and said gates associated with the first and second channel regions are electrically interconnected. During operation non-semiconductor components of electrically non-interconnected rectifying (Schottky barrier) source junctions are held at different voltages, and application of a gate voltage affects semiconductor channel region doping type in both said first and second channel regions, and thus which electrically non-interconnected rectifying (Schottky barrier) source junction forward conducts and which does not forward conduct, thereby controlling the voltage present at the electrically interconnected essentially non-rectifying source junctions through said forward conducting rectifying (Schottky barrier) junction. In said non-inverting gate voltage channel induced semiconductor device an increase in applied Gate voltage leads to an increase in the voltage appearing at the electrically interconnected essentially non-rectifying source junctions. It is to be noted that said essentially non-rectifying source junctions are present xe2x80x9cbetweenxe2x80x9d said first and second channel regions, as said term xe2x80x9cbetweenxe2x80x9d is utilized herein.
Where Intrinsic or substantially compensated, (approximately equal amounts of both N and P-type metalurgical dopants present), semiconductor is utilized, the description is beneficially slightly revised. Said non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems formed in a essentially essentially intrinsic or substantially compensated semiconductor substrate still comprises two junctions, termed source and drain, which are separated by a first semiconductor channel region, and still further comprises two additional junctions, termed source and drain, which are separated by a second semiconductor channel region. Gates to which semiconductor channel region effecting voltage can be applied are still associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use, application of sufficient positive voltage to said gates still attracts electrons to said first and second semiconductor channel regions, and application of sufficient negative voltage to said gates still attracts holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each potentially essentially non-rectifying when sufficient field-induced doping is attracted into said first and second channel regions, and which drain junctions are potentially rectifying (Schottky barrier) junctions when sufficient field-induced doping is attracted into said first and second channel regions. Again assuming said potentially rectifying junctions are Schottky barrier junctions which each comprise a semiconductor and non-semiconductor component, in the non-inverting gate voltage channel induced semiconductor device the potentially non-rectifying source junction associated with said first channel region and the potentially non-rectifying source junction associated with the second channel region are electrically interconnected, and said gates associated with the first and second channel regions are electrically interconnected. During operation non-semiconductor components of electrically non-interconnected potentially rectifying (Schottky barrier) drain junctions are held at different voltages, and application of a gate voltage affects semiconductor channel region doping type in both said first and second channel regions, and thus which electrically non-interconnected rectifying (Schottky barrier) source junction forms and forward conducts and which does not, thereby controlling the voltage present at the formed electrically interconnected essentially non-rectifying source junctions, through said forward conducting rectifying (Schottky barrier) junction. In said non-inverting gate voltage channel induced semiconductor device an increase in applied Gate voltage leads to an increase in the voltage appearing at the electrically interconnected essentially non-rectifying source junctions which form. It is to be noted that said essentially non-rectifying source junctions are present xe2x80x9cbetweenxe2x80x9d said first and second channel regions, as said term xe2x80x9cbetweenxe2x80x9d is utilized herein.
The basis of operation of both said inverting and non-inverting gate voltage channel induced semiconductor devices is that said (Schottky barrier) junctions are formed from said first and second semiconductor channel regions and material(s) which provide a rectifying junction to a semiconductor channel region when it is doped either N or P-type, whether said doping is achieved via metallurgical or field induced means.
In both said inverting and non-inverting gate voltage channel induced semiconductor devices the electrically interconnected drain, or electrically interconnected source, junctions comprise an essentially electrically isolated, (from said gates), terminal, and said electrical interconnection between sources, (non-inverting case), or drains, (inverting case), can be considered to be electrically interconnected to a separate or essentially integrated thereinto essentially electrically isolated terminal. In particular said xe2x80x9cessentially electrically isolated terminalxe2x80x9d can be an integral indistinguishable unit with an electrical interconnection between non-semiconductor components of a Schottky barrier junction which are present outside of, (ie. xe2x80x9cbetweenxe2x80x9d), first and second channel regions in an inverting single device with operating characteristics similar to multiple device (CMOS) systems, or similarly, with ohmic junctions between first and second channel regions. Such an xe2x80x9cessentially electrically isolated terminalxe2x80x9d can also be considered to contact said electrically interconnected sources or drains by a xe2x80x9cjunctionxe2x80x9d thereto. The concept of an essentially electrically isolated terminal is identified as it provides analogy to conventional (CMOS), but as in conventional (CMOS) its discrete presence is not pivotal. Also, it is specifically noted that the word xe2x80x9cbetweenxe2x80x9d does not imply a physical, geometrical direct placement of a junction or other contact, but rather refers more to an electrical continuity with junction components xe2x80x9coutsidexe2x80x9d of both channel regions per se. For instance, a junction placed to the right or left or top or bottom of first and/or second channel regions which are located vertically one above the other, is still xe2x80x9cbetweenxe2x80x9d said first and second channel regions, as it is not within said first or second channel regions. Said otherwise, any geometrical location of any channel regions, contact(s) or junction(s) etc., consistent with described functional operation of single device:equivalents to multiple device (CMOS) is to be considered within the scope of claimed invention, emphasis added.
Continuing, an alternative description of an inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, provides that said inverting gate voltage channel induced semiconductor device be formed in a single doping type, (ie. no requirement of both N and P-type regions), semiconductor substrate which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), or functional combinations thereof; and comprise two junctions, termed source and drain, which are separated by a first semiconductor channel region, and further comprise two additional junctions, termed source and drain, which are separated by a second semiconductor channel region. Gates, to which semiconductor channel region doping effecting voltage can be applied, are associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use application a sufficient positive voltage to said gates will attract electrons to said first and second semiconductor channel regions, and such that application of sufficient negative voltage to said gates will attract holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each essentially non-rectifying, and which drain junctions are rectifying junctions. In said inverting gate voltage channel induced semiconductor device the rectifying drain junction associated with said first semiconductor channel region is electrically interconnected with the rectifying drain junction associated with said second semiconductor channel region, and said gates associated with said first and second channel regions are electrically interconnected. During operation the electrically non-interconnected essentially non-rectifying source junctions are held at different voltages, and application of a gate voltage affects semiconductor channel region doping type in both said first and second channel regions, and thus which electrically interconnected rectifying drain junction forward conducts and which does not forward conduct, thereby controlling the voltage present at the electrically interconnected rectifying drain junctions essentially through said forward conducting rectifying drain junction. The basis of operation of said inverting gate voltage channel induced semiconductor device is that said rectifying drain junctions associated with said first and second semiconductor channel regions thereof are comprised of material(s) that form a rectifying junction to a semiconductor channel region when it is doped either N or P-type by either metallurgical or field induced means.
An alternative description of a non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, provides that said non-inverting gate voltage channel induced semiconductor device is formed in a single doping type, (ie. no requirement of both N and P-type regions), semiconductor substrate which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), or functional combinations thereof; and comprises two junctions, termed source and drain, which are separated by a first semiconductor channel region, and further comprises two additional junctions, termed source and drain, which are separated by a second semiconductor channel region, wherein gates, to which semiconductor channel region doping effecting voltage can be applied, are associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use application a sufficient positive voltage to said gates will attract electrons to said first and second semiconductor channel regions, and application of sufficient negative voltage to said gates will attract holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each essentially non-rectifying, and which drain junctions are rectifying junctions. The essentially non-rectifying source junction associated with said first channel region and the essentially non-rectifying source junction associated with the second channel region are electrically interconnected, and in which said gates associated with said first and second channel regions are electrically interconnected. During operation the electrically non-interconnected rectifying drain junctions are held at different voltages, and application of a gate voltage affects semiconductor channel region doping type in both said first and second channel regions, and thus which electrically non-interconnected rectifying drain junction forward conducts and which does not forward conduct, thereby controlling the voltage present at the electrically interconnected essentially non-rectifying source junctions through said forward conducting rectifying drain junction. The basis of operation of said non-inverting gate voltage channel induced semiconductor devices being that said rectifying drain junctions associated with said first and second semiconductor channel regions thereof are comprised of material(s) that form a rectifying junction to a semiconductor channel region when it is doped either N or P-type by either metallurgical or field induced means.
As another alternative description of a non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, said non-inverting gate voltage channel induced semiconductor device is formed in a single doping type, (ie. no requirement of both N and P-type regions), semiconductor substrate which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), or functional combinations thereof; and comprises two junctions, termed source and drain, which are separated by a semiconductor channel region, wherein a gate, to which semiconductor channel region doping effecting voltage can be applied, is associated with said semiconductor channel region, said gate being offset from said semiconductor channel region by insulating material. During use application a sufficient positive voltage to said gate will attract electrons to said semiconductor channel region, and application of sufficient negative voltage to said gate will attract holes to said semiconductor channel region, the purpose of applying such gate voltage being to affect the effective doping type of said semiconductor channel region between said source and drain junctions, which source and drain junctions are both rectifying junctions. Said non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems further comprises an electrical contact to said channel region. During operation the rectifying source and drain junctions are held at different voltages, and application of a gate voltage affects semiconductor channel region doping type in said channel region, and thus which rectifying junction forward conducts and which does not forward conduct, thereby controlling the voltage present at the electrical contact to said channel region essentially through said forward conducting rectifying junction. Again, the basis of operation of said non-inverting gate voltage channel induced semiconductor device being that said rectifying junctions associated with a semiconductor channel region are comprised of material(s) that form a rectifying junction to semiconductor channel region when it is doped either N or P-type by either metallurgical or field induced means.
Another description of the present invention inverting and non-inverting devices with operating characteristics similar to dual device seriesed N and P-Channel MOSFETS CMOS systems provides that in use, two oppositely facing electrically interconnected rectifying diodes in essentially intrinsic, or substantially compensated, or a single doping type, (ie. no requirement of both N and P-type regions), semiconductor substrate which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), and functional combinations thereof; and are formed, each of said electrically interconnected rectifying diodes having an accessible terminal. A forward direction of rectification of each of said electrically interconnected rectifying diodes changes depending upon what doping type, (N or P), be it metallurgically or field induced, is present in the semiconductor, said inverting and non-inverting single device equivalents to dual device seriesed N and P-Channel MOSFETS CMOS systems further comprises gate means for field inducing effective doping type in said semiconductor, said gate means being set off from said semiconductor by insulator; wherein, in use, different voltages are applied to each accessible terminal of each of the oppositely facing rectifying diodes, and a voltage between said applied different voltages, inclusive, is monitored at the electrical interconnection between said two oppositely facing rectifying diodes, which monitored voltage responds as a function of applied gate voltage, said monitored voltage being essentially electrically isolated from said gate voltage and appearing at said electrical interconnection between said two oppositely facing rectifying diodes primarily through the rectifying diode selected from the group consisting of: (said two oppositely facing electrically interconnected rectifying diodes), which is caused to be forward biased as a result of semiconductor doping type modulation by said applied gate voltage.
A present invention semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems can also be described as being formed in a semiconductor substrate which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), and functional combinations thereof; and comprising at least one rectifying junction which is formed from non-semiconductor substrate and semiconductor substrate components, wherein said junction non-semiconductor substrate component is comprised of material(s) which, in use, form a rectifying junction with either N and P-type semiconductor, whether metallurgically or field induced.
Another description of a present invention inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, provides that said inverting gate voltage channel induced semiconductor device be formed in an essentially intrinsic or substantially compensated or single doping-type, (ie. no requirement of both N and P-type regions), semiconductor substrate and comprise two junctions, termed source and drain, which are separated by a first semiconductor channel region, and further comprise two additional junctions, termed source and drain, which are separated by a second semiconductor channel region. Gates, to which semiconductor channel region effecting voltage can be applied, are associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use application a sufficient positive voltage to said gates will attract electrons to said first and second semiconductor channel regions, and such that application of sufficient negative voltage to said gates will attract holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each essentially non-rectifying when sufficient gate voltage induced doping is present in the channel region adjacent thereto, and which drain junctions are rectifying junctions when sufficient gate voltage induced doping is caused to be present in the channel region adjacent thereto. A rectifying drain junction associated with said first semiconductor channel region is electrically interconnected with a rectifying drain junction associated with said second semiconductor channel region, and in which said gates are electrically interconnected. During operation the electrically non-interconnected essentially non-rectifying source junctions are held at different voltages, and application of a gate voltage selected from the group consisting of: (positive and negative), affects semiconductor channel region doping type in said first and second channel regions to be a selection from the group consisting of: (essentially non-conductive essentially intrinsic and substantially compensated and doped to the same type selected from the group consisting of: (N-type and P-type), at doping levels selected from the group consisting of: (essentially equal and different)); and thus which electrically interconnected rectifying drain junction in said single doping type, (ie. no requirement of both N and P-type regions), semiconductor substrate forms and forward conducts, thereby controlling the voltage present at the electrically interconnected rectifying drain junctions essentially through said formed forward conducting rectifying drain junction. The basis of operation is that said rectifying junctions associated with said first and second semiconductor channel regions are comprised of materials that form a rectifying junction to a semiconductor channel region when it is caused to be doped either N or P-type by either metallurgical or field induced means.
It is further noted that the described semiconductor substrate channel region and junction which is not forward conducting is characterized by at least one selection from the group consisting of:
a. being an essentially essentially intrinsic or substantially compensated channel region;
b. being functionally comprised of two regions across which voltage can drop, namely an onset of pinch-off region and an essentially essentially intrinsic or substantially compensated channel region;
c. being functionally comprised of three regions across which voltage can drop, namely an onset of pinch-off region, a portion of the channel region which is populated with some gate voltage induced carriers, and a reverse biased rectifying junction.
Also, the inverting gate voltage channel induced semiconductor device semiconductor substrate channel region and adjacent junction which is forward conducting is characterized as comprising a doped channel region and a forward biased junction.
Another description of a present invention non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, said non-inverting gate voltage channel induced semiconductor device being.formed in an essentially intrinsic or substantially compensated or single doping-type, (ie. no requirement of both N and P-type regions), semiconductor substrate and comprising two junctions, termed source and drain, which are separated by a first semiconductor channel region, and further comprising two.additional junctions, termed source and drain, which are separated by a second semiconductor channel region. Gates, to which semiconductor channel region effecting voltage can be applied, are associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use application a sufficient positive voltage to said gates will attract electrons to said first and second semiconductor channel regions, and application of sufficient negative voltage to said gates will attract holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each essentially non-rectifying when sufficient gate voltage induced doping is present in the channel region adjacent thereto, and which drain junctions are rectifying junctions when sufficient gate voltage induced doping is caused to be present in the channel region adjacent thereto. In said non-inverting gate voltage channel induced semiconductor device the potentially essentially ohmic source junction associated with said first semiconductor channel region is electrically interconnected with a the potentially ohmic source junction associated with said second semiconductor channel region, and in which said gates are electrically interconnected. During operation the electrically non-interconnected potentially rectifying drain junctions are held at different voltages, and application of a gate voltage selected from the group consisting of: (positive and negative), affects semiconductor channel region doping type in said first and second channel regions to be a selection from the group consisting of: (essentially non-conductive essentially intrinsic and substantially compensated and doped to the same type selected from the group consisting of: (n-type and p-type), at doping levels selected from the group consisting of: (essentially equal and different)); and thus controls formation of a forward conducting rectifying drain junction in said semiconductor substrate, thereby controlling the voltage present at the electrically interconnected potentially ohmic source junctions essentially through said formed forward conducting rectifying junction. The basis of operation being that essentially intrinsic or substantially compensated semiconductor is essentially non-conductive but that said rectifying junctions associated with said first and second semiconductor channel regions are comprised of material(s) that form a rectifying junction to a semiconductor channel region when it is caused to be doped either N or P-type by field induced means.
The semiconductor substrate channel region and adjacent rectifying junction which is not forward conducting is characterized by at least one selection from the group consisting of:
a. being an essentially essentially intrinsic or substantially compensated channel region;
b. being functionally comprised of two regions across which voltage can drop, namely a portion of the channel region which is populated with some gate voltage induced carriers, and a reverse biased rectifying junction.
The semiconductor substrate channel region and adjacent rectifying junction which is forward conducting is characterized as comprising a field induced doped channel region and a forward biased rectifying junction.
Any of the above described inverting and non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems can further comprise a voltage bias source connected across said electrically non-interconnected essentially non-rectifying source junctions so that, they are held at different voltages, said voltage bias source optionally providing contact to the back of said semiconductor substrate.
A present invention modulator is described as comprising in use, two oppositely facing electrically interconnected rectifying diodes in a semiconductor substrate which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contain a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed with no requirement of alternating N and P-type regions), and functional combinations thereof; each of said electrically interconnected rectifying diodes having an accessible terminal, wherein a forward direction of rectification of each of said electrically interconnected rectifying diodes changes depending upon what doping type, (N or P), be it metallurgically or field induced, is present in the semiconductor. Said modulator further comprises gate means for field inducing effective doping type in said semiconductor, said gate means being set off from said semiconductor by insulating material, such that during use application a sufficient positive voltage to said gate will attract electrons to said semiconductor channel region, and such that application of sufficient negative voltage to said gate will attract holes to said semiconductor channel region, the purpose of applying such gate voltage being to affect the effective doping type of said semiconductor channel region between the source and drain junctions, said source junction being essentially non-rectifying, and said drain junction being rectifying, and each of said electrically interconnected rectifying diodes having a non-electrically interconnected terminal, such that, in use, a varying voltage is applied between the non-electrically interconnected terminals of the oppositely facing rectifying diodes, and a varying voltage is monitored at the electrical interconnection between said two oppositely facing rectifying diodes, which monitored varying voltage is a modulated function of said varying voltage applied between the non-electrically interconnected terminals of the oppositely facing rectifying diodes and a varying applied gate voltage, said monitored varying voltage being essentially electrically isolated from said varying applied gate voltage and appearing at said electrical interconnection between said two oppositely facing rectifying diodes primarily through one of said oppositely facing rectifying diodes which is caused to be forward biased as a result of semiconductor doping type modulation caused by application of said varying gate voltage.
A present invention gate voltage channel induced semiconductor device with operating characteristics similar to a non-latching SCR, can be described as a gate voltage channel induced semiconductor device being formed in a semiconductor substrate which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), or functional combinations thereof, and comprising two junctions, termed source and drain, which are separated by a semiconductor channel region, wherein a gate, to which semiconductor channel region doping effecting voltage can be applied, is associated with said semiconductor channel region, said gate being offset from said semiconductor channel region by insulating material. During use application a sufficient positive voltage to said gate will attract electrons to said semiconductor channel region, and application of sufficient negative voltage to said gate will attract holes to said semiconductor channel region, the purpose of applying such gate voltage being to affect the effective doping type of said semiconductor channel region between the source and drain junctions, said source junction being essentially non-rectifying, and said drain junction being rectifying. Said gate voltage channel induced semiconductor device with operating characteristics similar to a non-latching SCR further comprises a source of voltage, such that during operation a voltage is applied therefrom across said source and drain junctions, and application of a gate voltage affects semiconductor channel region doping type in said channel region, and thus if said rectifying drain junction forward conducts or does not forward conduct, thereby controlling the flow of current through rectifying drain junction between reverse bias and forward bias levels. Again, the basis of operation is that said rectifying drain junction is comprised of material(s) that form a rectifying junction to a semiconductor channel region when it is doped either N or P-type by either metallurgical or field induced means.
In any of the described present invention semiconductor devices, (eg. inverting and non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, modulators and non-latching SCR""s), at least one present junction (eg. source or drain), can be characterized by at least one selection from the group consisting of: (being formed in a region etched into the semiconductor, being formed by a process comprising vacuum deposition of said material(s) onto said semiconductor, being formed by a .process comprising diffusion of said material(s) into said semiconductor, being formed by a process comprising ion-implantation of said material(s) into said semiconductor, and being comprised of material(s) which form a barrier height of approximately half the band-gap of the semiconductor and being formed in silicon semiconductor).
In any of the described present invention semiconductor devices, (eg. inverting and non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, modulators and non-latching SCR""s), the semiconductor substrate can further comprise at least one region of parasitic current flow blocking material therein which is optionally physically separate from the semiconductor device and prevents parasitic currents from flowing to or away therefrom through said region of parasitic current flow blocking material; which at least one region of parasitic current flow blocking material forms rectifying junctions with both N and P-type field induced semiconductor.
It is emphasized that any of the foregoing described devices can be formed in regions of semiconductor substrates characterized by being:
essentially intrinsic; or
essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, (ie. be substantially compensated); or
essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or
containing a single metallurgical doping type, or be lightly metallurgically doped, or
functional combinations thereof.
Continuing, it is also noted that an inverting gate voltage channel induced semiconductor device can be fabricated by a five mask procedure comprising, in a functional order, the steps of:
a. providing a silicon substrate selected from the group consisting of: (essentially intrinsic and substantially compensated and doped);
b. growing a depth of silicon dioxide atop thereof for use as a gate oxide adjacent to a gate voltage field induced channel region;
c. optionally implanting N or P-type channel doping regions;
d. etching two source openings through said silicon dioxide to
e. depositing aluminum atop the silicon dioxide such that it contacts the silicon through the two etched source openings;
f. etching an xe2x80x9c8xe2x80x9d shaped pattern around the sources through the aluminum and silicon dioxide to the silicon so that one source is present in each of said regions of said xe2x80x9c8xe2x80x9d shaped pattern using a second mask and photolithography techniques, (or alternatively etching only a region between the two source openings from step d.);
g. optionally continuing said etch performed in step f. into said silicon;
h. depositing a material which forms rectifying junctions with either N or P-type silicon when in contact therewith and annealed, and annealing to form rectifying junctions where said deposited material contacts said silicon;
i. by selective acid etching removing un-reacted material which was deposited in step h.;
j. delineating the sources from the gates which surround each of said sources and which are surrounded by said etched xe2x80x9c8xe2x80x9d pattern, said gates being the aluminum deposited in step e. and remaining present between each said source and said xe2x80x9c8xe2x80x9d shaped pattern using a third mask and photolithography techniques, (or alternatively around the region between the two source openings from step d.);
k. depositing insulator over the entire surface of the structure;
l. etching openings through said insulator to provide access the gates, sources and xe2x80x9c8xe2x80x9d shaped region, (or alternatively etching only a region between the two source openings from step d.), using a forth mask and photolithography techniques;
m. depositing aluminum over the entire surface of the deposited insulator;
n. etching said aluminum deposited in step m. to delineate two sources, xe2x80x9c8xe2x80x9d, (or alternatively only a region between the two source openings from step d.) and gate contact pads using a fifth mask and photolithography techniques; and
o. optionally performing a sinter anneal so that aluminum deposited in step m. and delineated into contact pads in step n. makes good electrical contact with regions etched open in step l. to access said gates, sources and said xe2x80x9c8xe2x80x9d shaped region, (or alternatively only a region between the two source openings from step d.).
A simpler, three mask fabrication procedure for Inverting Single Device CMOS is:
a. select essentially intrinsic or substantially compensated silicon as a semiconductor and grow a gate enabling depth, (eg. 10 to thousands of Angstroms), of silicon dioxide atop thereof;
b. use a first Mask to open an xe2x80x9c8xe2x80x9d shape through the silicon dioxide to the silicon, possibly including undercutting of the silicon dioxide, said xe2x80x9c8xe2x80x9d shape having width and being accessable at the midpoint between the sides of the xe2x80x9c8xe2x80x9d shape;
c. deposit a material, (eg. chromium), which when annealed in contact with silicon forms a junction which is rectifying with either N or P-type filed induced silicon, then anneal and then rinse off unreacted deposited, (eg. where chromium is utilized a mixture of perchloric acid and cerric ammonium nitrate and water works well);
d. using a second mask open regions inside each side of the xe2x80x9c8xe2x80x9d shape to the silicon, optionally including a step to rough up the silicon surface so as to enhance the ability to form an ohmic junction therewith;
e. deposit a material, (eg. aluminum) over the entire surface of the essentially intrinsic or substantially compensated silicon.
f. using a third mask delineate device regions inside each side of the xe2x80x9c8xe2x80x9d shape from the surrounding regions, and to delineate the material which contacts the midpoint between the sides of the xe2x80x9c8xe2x80x9d shape from each of the sides of the xe2x80x9c8xe2x80x9d shape.
A non-inverting gate voltage channel induced semiconductor device can be fabricated by a procedure comprising, in a functional order, the steps of:
a. providing a silicon substrate selected from the group consisting of: (essentially intrinsic and substantially compensated and doped);
b. growing a depth of silicon dioxide atop thereof for use as a gate oxide adjacent to a gate voltage field induced channel region;
c. optionally implanting N or P-type channel doping regions;
d. etching an xe2x80x9c8xe2x80x9d shaped pattern through said silicon dioxide to the silicon using a first mask and photolithography techniques;
e. depositing aluminum atop the silicon dioxide such that it contacts the silicon through said etched silicon dioxide;
f. etching open drain regions inside each of said xe2x80x9c8xe2x80x9d shaped pattern regions etched open in step d. through said aluminum and silicon dioxide to the silicon using a second mask and photolithography techniques;
g. optionally continuing said etch performed in step f. into said silicon;
h. depositing a material which forms rectifying junctions with either N or P-type silicon when in contact therewith and annealed, and annealing to form rectifying junctions where said deposited material contacts said silicon;
i. by selective acid etching removing un-reacted material which was deposited in step h.;
j. delineating the gates which surround each of said drains from the surrounding etched xe2x80x9c8xe2x80x9d pattern, said gates being the aluminum deposited in step e. and remaining present between each said drain and said xe2x80x9c8xe2x80x9d shaped pattern using a third mask and photolithography techniques;
k. depositing insulator over the entire surface of the structure;
l. etching openings through said insulator to provide access said gates, drains and said xe2x80x9c8xe2x80x9d shaped region using a forth mask and photolithography techniques;
m. depositing aluminum over the entire surface of the deposited insulator;
n. etching said aluminum deposited in step m. to delineat two drains, xe2x80x9c8xe2x80x9d and gate contact pads using a fifth mask and photolithography techniques; and
o. optionally performing a sinter anneal so that aluminum deposited in step m. and delineated into contact pads in step n. makes good electrical contact with regions etched open in step l. to access said gates, drains and said xe2x80x9c8xe2x80x9d shaped region.
(As for the case of the inverting gate voltage channel induced semiconductor device fabrication procedure, the xe2x80x9c8xe2x80x9d shaped region can be replaced by a simple opening between what are the drain openings opened in step f.).
It is to be particularly appreciated that no high cost diffusions are required in the above demonstrative, non-limiting fabrication procedures, and that only five photolithographic masking steps are required in each. Any metallurgical doping can be entered during ingot growth. The optional ion implants, (when performed), serve to provide a channel depth region of doping and effectively form a doped semiconductor on insulator (the insulator being the essentially intrinsic or substantially compensated semiconductor region beyond the channel region), system where essentially intrinsic or substantially compensated semiconductor is initially present. It is to be understood that current flow limiting, device isolating, non-conductive essentially intrinsic or substantially compensated silicon is preferred, though not limiting, as the beginning semiconductor system for gate voltage channel induced semiconductor devices and that purely field induced doping is sufficient for operability thereof. The presence of both N and P-type dopants in a semiconductor substrate makes it easier to ionize both electrons and holes by applied Gate Voltage.
It is also to be understood that fabrication procedures other than those described can also be practiced to the end that present invention inverting or non-inverting gate voltage channel induced semiconductor devices are realized, and that said resulting present invention inverting or non-inverting gate voltage channel induced semiconductor devices remain within the scope of the present invention.
It is also noted that the present invention has application to semiconductor devices formed In Gallium-Arsenide, as well as in Silicon. In particular it is difficult to dope GaAs greater than about 1018 per cm3, and aluminum does not form a good ohmic junction to semiconductor doped less than about 1020 per cm3 This greatly limits realization of devices in GaAs. However, while it is difficult to form high metallurgical concentrations in N-type GaAs, It Is noted that field induced concentrations can be formed In MOSFET-type channel regions, and a highly concentrated channel region adjacent to a metal contact can be driven to be essentially ohmic by application of a sufficiently high, channel region Inducing, Gate voltage. The same effect, of course, is available to devices formed In Silicon, and other semiconductors.
Also, it is noted that copper or other metal can replace aluminum in the recited demonstrative, non-limiting fabrication procedures, and that additional steps can include deposition of materials to help secure deposited metals and formed silicides etc. In fact, a few percent copper in aluminum can greatly reduce electromigration effects which can degrade devices in which aluminum is used as a contact metal in semiconductor devices. Further, polysilicon, ferroelectric containing insulator and other type gates can be formed in place of metal gates in present invention semiconductor devices. Further, the present invention comprises a semiconductor system comprising a semiconductor device in a semiconductor substrate characterized by being essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; and containing a single metallurgical doping type, substantially compensated, or lightly doped, or functional combinations thereof;
said semiconductor device comprising at least one junction(s) selected from the group consisting of:
P-N rectifying;
Schottky barrier rectifying; and
formed from non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component of said at least one function(s) is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced; and
wherein the semiconductor system further comprises at least one region of parasitic current flow blocking material in said semiconductor substrate, which is physically separate from the semiconductor device and which serves to prevent significant parasitic currents from flowing therethrough when a voltage is present thereacross; wherein said at least one region of parasitic current flow blocking material is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether metalurigically or field induced.
Said semiconductor system comprising a semiconductor device in a semiconductor substrate can be associated with a semiconductor device which comprises a plurality of junctions arranged as, for instance, a selection from the group consisting of a-j, where said a.-j. are:
a.
being essentially ohmic; and
comprising non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced.
b.
comprising non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced; and
comprising non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced;
c.
being essentially ohmic;
comprising non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced; and
comprising non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced; and
being essentially ohmic;
d.
being substantially ohmic;
being rectifying;
being rectifying; and
being substantially ohmic.
e.
comprising non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying.junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced;
being essentially ohmic;
being essentially ohmic; and
comprising non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced;
f.
being essentially ohmic; and
being rectifying P-N;
g.
being rectifying P-N; and being rectifying P-N;
h.
being essentially ohmic;
being rectifying P-N;
being rectifying P-N; and
being essentially ohmic;
i.
being rectifying P-N;
being essentially ohmic;
being essentially ohmic; and
being rectifying P-N;
j.
being rectifying; and
being rectifying.
The present invention will be better understood by reference to the Detailed Description Section of this Disclosure, in conjunction with the accompanying Drawings.
It is a purpose and/or objective of the present invention to provide examples of application of material which forms rectifying junctions with either N or P-type semiconductor.
It is another purpose and/or objective yet of the present invention to describe semiconductor devices, the operational basis of which relies upon the fact that certain materials form rectifying junctions with either N or P-type doped semiconductor, whether metallurgical or field induced, in a manner which compliments the description found in U.S. Pat. Nos. 5,663,584; 5,760,449 and 6,091,128 to Welch.
It is a further purpose and/or objective yet of the present invention to teach simple fabrication procedures for inverting and non-inverting gate voltage channel induced semiconductor devices which have operating characteristics similar to inverting and non-inverting multiple device conventional (CMOS) systems.
It is yet another purpose and/or objective of the present invention to make clear that any rectifying or ohmic junction structure geometry, whether present in a region etched into semiconductor or not, and that any gate structure, metal or polysilicon, ferroelectric material containing insulator etc. is within the scope of present invention gate voltage channel induced semiconductor devices which have operating characteristics similar to inverting and non-inverting multiple device conventional (CMOS) systems.
It is still yet another purpose and/or objective of the present invention to describe biasing and operational characteristics of semiconductor devices which utilize.materials which form rectifying junctions with either N or P-type semiconductor, and in particular to describe such operation of inverting gate voltage channel induced semiconductor devices formed in a region of a semiconductor substrate characterized by being essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, (ie. substantially compensated), or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, or containing a single metallurgical doping type at a light or heavy doping level, (eg. 1012 to 1019 per centimeter cubed), and functional combinations thereof; said semiconductor devices having operating characteristics similar to inverting multiple device conventional (CMOS).
It is a further purpose and/or objective of the present invention to make clear that the preferred embodiment thereof includes inverting and non-inverting single device equivalents to dual device seriesed N and P-Channel MOSFETS CMOS systems formed in semiconductor substrates that do not require the presence of alternating N and P-type doping regions and which comprise two oppositely facing rectifying diodes in essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, (ie. substantially compensated), or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, or containing a single doping type at light or heavy metallurgical doping levels, and functional combinations thereof; wherein said rectifying diode direction of rectification changes depending upon what doping type, (N or P), be it metallurgically or field induced, is present in the semiconductor, said inverting and non-inverting single device equivalents to dual device seriesed N and P-Channel MOSFETS CMOS systems further comprising gate means for field inducing effective doping type in said semiconductor, and wherein a voltage monitored at an electrical contact between said rectifying diodes responds as a function of applied gate voltage, but is essentially electrically isolated therefrom.
It is a further purpose and/or objective still of the present invention to make clear that a semiconductor device in a semiconductor substrate, comprising at least one junction which is formed from non-semiconductor substrate and semiconductor substrate components, wherein said junction non-semiconductor substrate component is comprised of material(s) which form a rectifying junction with either N or P-type semiconductor, whether metallurgically or field induced, can be fabricated by any functional technique, (eg. procedures comprising vacuum deposition, ion-implantation and/or dopant deposition and diffusion, optionally combined with any accompanying anneals etc.), and remain within the scope of the present invention.
It is another purpose and/or objective of the present invention to describe application of material(s) which form rectifying junctions with either N or P-type semiconductor to provide modulators and non-latching SCR""s in regions of semiconductor substrates characterized as essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, (ie. substantially compensated), or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, or containing a single doping type at light or heavy metallurgical doping levels, and functional combinations thereof.
It is yet another purpose and/or objective of the present invention to describe the prevention of parasitic current flows in semiconductor substrates containing semiconductor devices comprised of P-N or Schottky barrier junctions by placing material(s) which form rectifying junctions with either N or P-type semiconductor, whether metallurgically or field induced, in the pathway of potential parasitic current flows.
Other purposes and/or objectives will be evident from a reading of the Disclosure and Claims.